Miniaturization of transistors has been developing to continually improve performance of transistors. Furthermore, it has also been adopted to reduce parasitic resistance in an extension area which is formed to be superposed on a source/drain region. In order to implement the reduction of the parasitic resistance, it is necessary to form the extension area so that the extension area is shallow and has low resistance and the concentration profile of impurities (dopant) is steep.
In order to activate impurities doped in a semiconductor substrate, an annealing treatment is performed on the semiconductor substrate. Rapid Thermal Annealing (RTA) of about 10 seconds in treatment time is used as the annealing treatment of the extension area. When RTA is used, thermal diffusion occurs in the doped impurities, and the junction of the extension area is formed deeply. In order to suppress the thermal diffusion, it is necessary to suppress the annealing temperature to a low value. However, when the annealing temperature is set to a low value, the activation rate of the impurities is lowered, and thus the sheet resistance increases.
Furthermore, Spike Annealing having a treatment time of about 0.1 second to 1 second and annealing treatments such as Flash Lamp Annealing and Laser Annealing which can heat a treatment target to a temperature larger than 1200° C. for an extremely short treatment time of about 1 m second (hereinafter referred to as msec annealing treatments) are known.
The semiconductor substrate is subjected to the above annealing treatment after a predetermined pattern is formed on the surface of the semiconductor substrate. Accordingly, the effective absorptance of energy is varied in accordance with the pattern due to light refraction, light reflection, etc. which are caused by the pattern. Therefore, when the surface state of the semiconductor substrate is different, the semiconductor substrate is not set to the same temperature even if the surface of the semiconductor substrate is irradiated with light having the same energy.
Therefore, there is disclosed a technique of calculating light reflectance of the surface of the semiconductor substrate as the treatment target prior to the annealing treatment, and controlling light irradiation of the annealing treatment by using the calculated reflectance (for example, see Japanese Laid-open Patent Publication Nos. 2007-13047, 2005-39213, 2005-207997). In Japanese Laid-open Patent Publication Nos. 2007-13047 and 2005-39213, when the light reflectance of the surface of the semiconductor substrate is calculated, only reflection light vertical to the surface concerned is detected. Furthermore, in Japanese Laid-open Patent Publication No. 2005-207997, when the light reflectance of the surface of the semiconductor substrate is calculated, only reflection light of a predetermined angle which corresponds to irradiation light of a predetermined angle to the surface concerned is detected. The irradiation light of a light source used for the annealing treatment is not collimated light, but light having a wide angle component.